The invention relates to an interpolation module, an interpolator, and methods capable of recovering timing, and in particular, to an interpolation module, an interpolator, and methods capable of recovering timing in a timing recovery apparatus of a receiver (e.g. orthogonal frequency division multiplexing receiver).
Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-channel modulation technology utilizing Fast Fourier Transform.(FFT) and Inverse Fast Fourier Transform (IFFT) to modulate and demodulate signals respectively with a plurality of orthogonal sub carriers. In an OFDM communication system, timing between an OFDM transmitter and an OFDM receiver is asynchronous. In order to recover timing, a timing recovery apparatus is utilized in the OFDM receiver.
FIG. 1 shows a block diagram illustrating a related art timing recovery apparatus 100. The timing recovery apparatus 100 comprises an analog-to-digital converter (ADC) 102, an interpolator 104, a FFT module 106, and a timing control module 108. The ADC 102 utilizes a reference sampling clock c, which is fixed and can be generated from a local oscillator (e.g. a PLL), to convert an analog input signal SA to a digital input signal SD that comprises a plurality of sampling values. Because the functionality and operation of the ADC 102 is known to those skilled in the art, further discussion of its operation is omitted for the sake of brevity. The interpolator 104 coupled to the ADC 102 interpolates the plurality of sampling values according to a fractional interval μk, which represents a duration of a timing error corresponding to a sample time k, to generate an interpolated signal S_INT that comprises a plurality of interpolants. A detailed description of the interpolator 104 is provided later. The FFT module 106 coupled to the interpolator 104 finally demodulates the interpolated signal S_INT to output a digital output signal S_OUT. The timing control module 108 coupled to the FFT module 106, the ADC 102, and the interpolator 104, generates the fractional interval μk to the interpolator 104 according to the digital output signal S_OUT and the digital input signal SD. The timing control module 108, acting like a related art digital phase locked loop (DPLL), comprises a timing error detector 110, a loop filter 112, and a timing controller 114. Since the timing control module 108 is known to those skilled in the art, further discussion is omitted for the sake of brevity. The operation of the interpolator 104 is further detailed in the following.
Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 2 is a circuit diagram illustrating the operation of the interpolator 104 shown in FIG. 1. FIG. 3 is a timing diagram showing a sample timing relation of the interpolator 104 shown in FIG. 2. The interpolator 104 is a piecewise-parabolic Farrow interpolator comprising delay modules 204, 206, 208, 210 and 212, a constant scale module 202, adders 214, 216, 218, 220, 222, 224, 226 and 228, and multiplers 230 and 232. The interpolator 104 utilizes the above-mentioned elements to interpolate the plurality of sampling values according to the fractional interval μk to generate the interpolated signal S_INT. The interpolated signal S_INT comprises a plurality of interpolants. One interpolant is shown below (please refer to FIG. 3 at the same time):S_INT[k]=SD[mk+2](−αμk+αμ2k)+SD[mk+1]((α+1)μk−αμ2k)+SD[mk](1−αμk−αμ2k)+SD[mk−1](−αμk+αμ2k)
Formula (1)
α is a predetermined parameter equal to 0.5, k is a sample time, and mk is another sample time corresponding to the sample time k. The predetermined parameter α equal to 0.5 simplifies the multiplication and reduces hardware design complexity. The predetermined parameter α is not however limited to 0.5. From FIG. 3, it can be seen that the sampling error corresponding to μk, which is generated from the timing control module 108, is equal to 1−μk. The detailed discussion of each element in the interpolator 104 is described in the following.
The delay modules 210 and 212 generate the sampling values SD[mk−1] and SD[mk−2] respectively through a sequential delay process according to the sampling value SD[mk]. It can be seen from formula (1) that the sampling value SD[mk−2] output from the delay module 212 is a zero order sampling value. The constant scale module 202 multiplies the sampling value SD[mk] by a negative constant equal to −0.5. The delay modules 204,206, and 208 then generate the plurality of sampling values −0.5*SD[mk−1], −0.5*SD[mk−2], and −0.5*SD[mk−3] respectively through the sequential delay process. The plurality of sampling values −0.5*SD[mk], −0.5*SD[mk−1], −0.5*SD[mk−2], and −0.5*SD[mk−3] are processed with the adders 214, 216, and 218, and the multipler 230 to generate a second order sampling value, which is output from the multipler 230. Similarly, the plurality of sampling values −0.5*SD[mk], −0.5*SD[mk−1], −0.5*SD[mk−2], −0.5*SD[mk−3], and SD[mk−1] are processed with the adders 220, 222, and 224 to generate a first order sampling value, which is output from the adder 224. The first and second order sampling values are added together with the adders 226 and multiplied by the fractional interval μk by the multipler 232. Finally, the zero order sampling value, which is generated from the delay module 212, is added to the sum of the first and second order sampling values, generated from the multipler 232, to generate the interpolant S_INT[k].
The related art interpolator 104 is commonly used for recovering timing in a timing recovery apparatus. Further detailed discussion of the related art interpolator can be found in Garder F. M., “Interpolation in Digital Modems—Part I: Fundamentals,” IEEE Trans. Commun., Vol. 41, No. 3, pp. 501-507, March 1993, and Erup L., Garder F. M., and Harris R. A., “Interpolation in digital modems—Part II : Implementation and Performance,” IEEE Trans. Commun., Vol 41, No. 6, pp. 998-1008, June 1993. However, in an N times sampling timing recovery (Ts=T/N, Ts is a sampling period and T is an OFDM symbol period), the Error Vector Magnitude (EVM) is worst when μk is equal to 1/2N. Please refer to FIG. 4. FIG. 4 is a constellation diagram of the digital output signal S_OUT wherein μk is equal to 0.125 and a sampling rate is equal to 4. When μk is equal to 1/2N, the constellation diagram (QPSK or QAM) has a wide spread, and hence decreases performance.